1. Field of the Invention
The present invention generally relates to semiconductor integrated circuits, and particularly relates to a semiconductor integrated circuit which latches input signals in synchronism with a clock signal.
2. Description of the Related Art
Semiconductor devices operating in synchronism with a clock signal receives a clock signal CLK as an input thereto, and uses this clock signal CLK for receiving other clock signals. In order to insure reliable data reading at rising edges of the clock signal CLK, data must become valid at least a setup time Ts before a given rising edge, and must be maintained at least for a duration of a hold time Th after the given rising edge. Required lengths of the setup time Ts and the hold time Th are generally specified in catalogs. Users need to make sure that the clock signal CLK and other signals are supplied to a semiconductor device so as to satisfy the setup time Ts and the hold time Th specified in the catalog.
When a clock cycle is 10 ns and the setup time Ts and the hold time Th are respectively 3 ns, for example, a data signal must maintain a valid value thereof during a 6-ns period centering at a given rising edge of the clock signal CLK.
In order to enhance operation speed of the semiconductor devices, a frequency of the clock signal CLK needs to be increased to boost data-input/output speed. When the clock cycle is shortened to 5 ns in comparison to the above example, however, the setup time Ts and the hold time Th proportionately become 1.5 ns, respectively. In this case, users are required to match a data-valid period with a 3-ns period of the setup time Ts and the hold time Th in terms of their temporal positions. In other words, the data signal must complete a signal-level change thereof within a 2-ns period output of the one clock cycle of 5 ns.
In this manner, as the frequency of the clock signal CLK is increased, an increased accuracy is required to the users with regard to timings of data supply. This results in more difficulties in system design and implementation.
In consideration of this, it is preferable to allow users to enjoy looser data-supply timings rather than requiring the users to comply with strict conditions of the setup time Ts and the hold time Th. When a clock cycle is 5 ns, for example, the loosest conditions for the users are achieved if data changes are allowed to take place within a 5-ns period which is the same as the clock cycle. Namely, if a semiconductor device is designed to latch data after a signal-level change thereof while allowing such a signal-level change to occur at any timing during a given one clock cycle, users are only required to position a data-change timing within one clock cycle, thereby making it easier to implement a system.
Accordingly, there is a need for a semiconductor integrated circuit which allows input-data changes to take place within a period of one clock cycle, and latches the input data after the signal changes thereof.